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HUF76113SK8
Data Sheet October 1999 File Number 4448.2
6.5A, 30V, 0.030 Ohm, N-Channel, Logic Level UltraFET Power MOSFET
This N-Channel power MOSFET is manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and batteryoperated products. Formerly developmental type TA76113.
Features
* Logic Level Gate Drive * 6.5A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.030 * Temperature Compensating PSPICETM Model * Temperature Compensating SABER Model * Thermal Impedance SPICE Model * Thermal Impedance SABER Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER HUF76113SK8 PACKAGE MS-012AA BRAND 76113SK8
Symbol
NC(1) DRAIN(8)
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76113SK8T.
SOURCE(2)
DRAIN(7)
SOURCE(3)
DRAIN(6)
GATE(4)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5 1 2 3 4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICETM is a trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HUF76113SK8
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified HUF76113SK8 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 4.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EASB Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 16 6.5 2.0 2.0 Figure 4 Figure 6 2.5 20 -55 to 150 300 260 W mW/oC
oC oC oC
UNITS V V V A A A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.76 in2 footprint at 10 seconds. 3. 177oC/W measured using FR-4 board with 0.0115 in2 footprint at 1000 seconds.
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, VGS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TA = 150oC
30 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance
IGSS
VGS = 16V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 11) ID = 6.5A, VGS = 10V (Figures 9, 10) ID = 2.0A, VGS = 5V (Figure 9) ID = 2.0A, VGS = 4.5V (Figure 9)
1 -
0.025 0.031 0.033
3 0.030 0.038 0.041
V
THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.76 in2 (Note 2) Pad Area = 0.054 in2 (See TB337) Pad Area = 0.0115 in2 (See TB337) SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 2.0A, RL = 7.5, VGS = 4.5V, RGS = 15 (Figure 15) 16 50 28 34 100 91 ns ns ns ns ns ns 50 143 177
oC/W oC/W oC/W
2
HUF76113SK8
Electrical Specifications
PARAMETER SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) 585 327 73 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VDD = 15V, ID 2.0A, RL = 7.5 VGS = 0V to 5V Ig(REF) = 1.0mA VGS = 0V to 1V (Figures 14) 17.5 10 0.65 1.10 5.40 21 12 0.78 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 6.5A, RL = 2.31, VGS = 10V, RGS = 16 (Figure 16) 6.5 33 45 40 59 126 ns ns ns ns ns ns TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD =6.5A ISD = 2.0A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 2.0A, dISD/dt = 100A/s ISD = 2.0A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.10 47 52 UNITS V V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 6 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
8 VGS = 10V, RJA = 50oC/W
4
VGS = 4.5V, RJA = 177oC/W
2
0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
3
HUF76113SK8 Typical Performance Curves
(Continued)
10
THERMAL IMPEDANCE
ZJA, NORMALIZED
1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
RJA = 50oC/W
0.1
PDM
t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 t, RECTANGULAR PULSE DURATION (s) 101 102 103
SINGLE PULSE 0.001 10-5 10-4 10-3
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500 TC = 25oC IDM, PEAK CURRENT (A) 100 VGS = 10V FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: VGS = 5V I
= I25
150 - TA 125
10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION
RJA = 50oC/W
1 10-5
10-4
10-3
10-2
10-1 t, PULSE WIDTH (s)
100
101
102
103
FIGURE 4. PEAK CURRENT CAPABILITY
500 TJ = MAX RATED TA = 25oC ID, DRAIN CURRENT (A) 100 100s 100 IAS, AVALANCHE CURRENT (A)
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10
STARTING TJ = 25oC
10
1ms
STARTING TJ = 150oC
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1
10ms VDSS(MAX) = 30V 100
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
1 0.01
0.1 1 10 tAV, TIME IN AVALANCHE (ms)
100
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
4
HUF76113SK8 Typical Performance Curves
30
(Continued)
30 -55oC 150oC 25oC 25 ID, DRAIN CURRENT (A) 20
VDD = 15V PULSE DURATION = 80s 25 DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) 20 15 10 5 0 0
VGS = 10V VGS = 5V VGS = 4.5V VGS = 4V
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 3.5V
15 VGS = 3V
10 5
0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5
0
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
150 ID = 6.5A NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID = 0.5A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 250s DUTY CYCLE = 0.5% MAX
2.0
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 6.5A
100 ID = 2A
1.5
50
1.0
0 0 6 8 2 4 VGS, GATE TO SOURCE VOLTAGE (V) 10
0.5 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 1.0 NORMALIZED GATE THRESHOLD VOLTAGE 1.0 0.9 0.8 0.7 0.6 -80 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A
1.2 ID = 250A
1.1
1.0
-40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
0.9 -80
-40
0 40 80 120 TJ , JUNCTION TEMPERATURE (oC)
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
5
HUF76113SK8 Typical Performance Curves
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 CRSS 0 0 5 10 15 20 25 30 VDS , DRAIN TO SOURCE VOLTAGE (V) CISS VGS , GATE TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
(Continued)
10 VDD = 15V 8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 6.5A ID = 2.0A ID = 0.5A 0 5 10 Qg, GATE CHARGE (nC) 15 20
COSS
2
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
120 VGS = 4.5V, VDD = 15V, ID = 2A, RL= 7.5 90 tr
150 VGS = 10V, VDD = 15V, ID = 6.5A, RL= 2.31 120 SWITCHING TIME (ns) tf td(OFF) 90 tf 60 tr
SWITCHING TIME (ns)
60 td(OFF)
30 td(ON)
30 td(ON)
0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
0
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
6
HUF76113SK8 Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORM
VDS RL VDD VDS VGS = 10 VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Ig(REF) 0 VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORMS
7
HUF76113SK8 Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJ(MAX), and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PD(MAX), in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJ(MAX) is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JMAX - T A ) P DMAX = --------------------------------------Z JA 250 RJA = 79.3 - 21.8*ln(AREA) 200 RJA (oC/W) 177 oC/W - 0.0115in2 143 oC/W - 0.054in2 150
(EQ. 1)
100
In using surface mount devices such as the SO-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of the PD(MAX) is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board 2. The number of copper layers and the thickness of the board 3. The use of external heat sinks 4. The use of thermal vias 5. Air flow and board orientation 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 23 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
50 0.001
0.01
0.1
1.0
AREA, TOP COPPER AREA (in2)
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
Displayed on the curve are the three RJA values listed in the Electrical Specifications table. The three points where chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PD(MAX). Thermal resistances corresponding to other component side copper areas can be obtained from Figure 23 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads.
R JA = 79.3 - 21.8 x ln ( Area ) (EQ. 2)
8
HUF76113SK8 PSPICE Electrical Model
SUBCKT HUF76113SK8 2 1 3 ;
CA 12 8 9.60-10 CB 15 14 9.95e-10 CIN 6 8 5.01e-10
10
REV 4 June 1998
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 32.3 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.00e-9 LGATE 1 9 1.00e-9 LSOURCE 3 7 2.27e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.01e-3 RGATE 9 20 2.94 RLDRAIN 2 5 10 RLGATE 1 9 10 RLSOURCE 3 7 2.27 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 17.50e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE CIN
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),2.5))} .MODEL DBODYMOD D (IS = 9.35e-13 RS = 1.39e-2 TRS1 = 1.12e-6 TRS2 = 1.05e-6 CJO = 9.85e-10 TT = 2.82e-8 M = 0.42 ) .MODEL DBREAKMOD D (RS = 1.91e-1 TRS1 = 3.51e-3 TRS2 = 1.21e-6 ) .MODEL DPLCAPMOD D (CJO = 5.51e-10 IS = 1e-30 N = 10 M = 0.60 ) .MODEL MMEDMOD NMOS (VTO = 1.76 KP = 3.55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.94) .MODEL MSTROMOD NMOS (VTO = 2.08 KP = 37 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.095 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 29.4 RS=0.1) .MODEL RBREAKMOD RES (TC1 = 1.02e-3 TC2 = 1.10e-7) .MODEL RDRAINMOD RES (TC1 = 4.05e-2 TC2 = 1.12e-4) .MODEL RSLCMOD RES (TC1 = 9.92e-3 TC2 = -2.06e-5) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -1.87e-3 TC2 = -5.42e-6) .MODEL RVTEMPMOD RES (TC1 = -1.12e-3 TC2 = 1.12e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -7.00 VOFF= -1.55) VON = -1.55 VOFF= -7.00) VON = 0.00 VOFF= 1.05) VON = 1.05 VOFF= 0.00)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
9
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
HUF76113SK8 SABER Electrical Model
nom temp=25 deg c HUF76113SK8 Ultrafet
REV 4 June 98 template HUF76113SK8 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is=9.35e-13, cjo= 9.85e-10,tt=2.82e-8, m=0.42) d..model dbreakmod = () d..model dplcapmod = (cjo=5.51e-10,is=1e-30,n=10,m=0.60) m..model mmedmod = (type=_n,vto=1.76,kp=3.55,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.08,kp=37,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.48,kp=0.095,is=1e-30, tox=1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-7.00,voff=-1.55) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.55,voff=-7.00) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=0,voff=1.05) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.05,voff=0) c.ca n12 n8 = 9.60e-10 c.cb n15 n14 = 9.95e-10 c.cin n6 n8 = 5.01e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1e-9 l.lsource n3 n7 = 2.27e-10
GATE 1 RLGATE CIN ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 MSTRO 8
LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED EBREAK + 17 18 71 RDBODY 5 DRAIN 2
6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
-
LSOURCE 7 RLSOURCE
SOURCE 3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.02e-3,tc2=1.10e-7 res.rdbody n71 n5 =1.39e-2, tc1=1.12e-6, tc2=1.05e-6 res.rdbreak n72 n5 =1.91e-1, tc1=3.51e-3, tc2=1.21e-6 res.rdrain n50 n16 = 2.01e-3, tc1=4.05e-2,tc2=1.12e-4 res.rgate n9 n20 = 2.94 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10 res.rlsource n3 n7 = 2.27 res.rslc1 n5 n51 = 1e-6, tc1=-9.92e-3,tc2=-2.06e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 17.5e-3, tc1=0,tc2=0 res.rvtemp n18 n19 = 1, tc1=-1.12e-3,tc2=1.12e-6 res.rvthres n22 n8 = 1, tc1=-1.87e-3,tc2=-5.42e-6 spe.ebreak n11 n7 n17 n18 = 32.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
RSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/180))** 2.5 )) } }
10
HUF76113SK8 SPICE Thermal Model (0.76 in2 footprint)
REV 3 June 1998 HUF76113SK8 CTHERM1 th 6 3.75e-4 CTHERM2 6 5 3.05e-3 CTHERM3 5 4 3.70e-2 CTHERM4 4 3 2.52e-2 CTHERM5 3 2 8.50e-2 CTHERM6 2 tl 7.95e-1 RTHERM1 th 6 3.95e-2 RTHERM2 6 5 2.50e-1 RTHERM3 5 4 4.00e-1 RTHERM4 4 3 6.35 RTHERM5 3 2 2.02e1 RTHERM6 2 tl 4.80e1
RTHERM1 CTHERM1 th JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model (0.76 in2 footprint)
SABER thermal model HUF76113SK8 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 3.75e-4 ctherm.ctherm2 6 5 = 3.05e-3 ctherm.ctherm3 5 4 = 3.70e-2 ctherm.ctherm4 4 3 = 2.52e-2 ctherm.ctherm5 3 2 = 8.50e-2 ctherm.ctherm6 2 tl = 7.95e-1 rtherm.rtherm1 th 6 = 3.95e-2 rtherm.rtherm2 6 5 = 2.50e-1 rtherm.rtherm3 5 4 = 4.00e-1 rtherm.rtherm4 4 3 = 6.35 rtherm.rtherm5 3 2 = 2.02e1 rtherm.rtherm6 2 tl = 4.80e1 }
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RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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